The NVIDIA Rubin Platform: Six New Chips, One AI Supercomputer

I’ve watched the industry push boundaries for years, and every once in a while a platform appears that reframes what’s possible. The NVIDIA Rubin Platform is one of those moments: a purpose-built AI supercomputer architecture that stitches together six new chips into a single, coherent system. It is engineered not as a collection of components, but as an integrated whole designed from the ground up to deliver massive AI performance at scale.

🚀 Why Rubin matters

This platform is about more than raw FLOPS. It reflects a philosophy of extreme co-design where CPU, GPU, networking, and offload processors were conceived to work as one. That changes the economics of training and inference for large models and sets a new bar for data-center AI infrastructure.

Here’s what stands out to me:

• Six purpose-built chips that are co-designed to share data coherently and bi-directionally.
• Huge system-level bandwidth so GPUs aren’t starved for data, with each GPU able to access terabits-per-second links.
• Thoughtful system packaging—compute trays with no cables, hoses, or fans—reducing complexity and improving reliability.
• Scale-out fabrics and photonics that let thousands of racks act like a single AI factory.

Put together, these advances deliver a platform capable of tackling the next generation of model sizes and multimodal workloads.

🧩 The architecture at a glance

At the heart of Rubin is an architectural principle I emphasize often: optimize at the system level, not just component by component. NVIDIA did that by co-designing the following elements to operate coherently:

• Vera (Vira) CPU—a new CPU designed to work tightly with Rubin GPUs.
• Rubin GPU—a GPU tuned for both training and inference at extreme scale.
• NVLink 6 / MV-Link switch—the sixth-generation high-speed switch for GPU-to-GPU communications.
• ConnectX-9 SuperNIC—high-bandwidth network interface controllers providing 1.6 terabits per second to each GPU.
• BlueField-4 DPU—a data processing unit that offloads storage, networking, and security tasks so compute stays focused on AI.
• Spectrum-X Ethernet with co-packaged optics—a photonics-enabled Ethernet switch that scales out thousands of racks.

These aren’t just components placed next to each other in a rack. They are engineered to exchange memory coherently and to offload non-AI work away from the GPUs so every watt of compute is used efficiently for model work.

🏗️ Inside the compute building block

The Rubin compute tray is the modular unit that gets deployed across racks and clusters. Its design choices are subtle but decisive.

Each tray contains a tight combination of processing and fabric elements:

• Two Vera CPUs working in tandem with the GPUs for host processing and system orchestration.
• Four Rubin GPUs providing the heavy lifting for model training and inference.
• BlueField-4 DPU to offload storage, IO, and security tasks.
• Eight ConnectX-9 NICs delivering massive scale-out bandwidth.

Two features stand out in how this tray is built:

1. It is designed with no cables, hoses, or fans. That reduces failure modes and makes it easier to scale and cool predictably.
2. High-speed robotics assemble complex boards with micro-level precision, placing around 17,000 components on a single Vira-Rubin compute board before final placement of CPUs and GPUs.

The result is a compact, reliable building block capable of delivering up to 100 petaflops of AI performance per their showcased module—roughly five times the prior generation.

🔬 Co-design: Vera CPU and Rubin GPU

I want to dig into the co-design between the Vera CPU and Rubin GPU. This relationship is central to the system’s efficiency.

Traditional data centers treat CPUs and GPUs as separate islands. CPU orchestrates, GPU computes. Moving data between them can be slow and costly. With Vera and Rubin, the two are architected to bi-directionally and coherently share data. That means they can access and move data faster, with far lower latency, and work from a consistent view of memory.

The practical benefits are immediate:

• Less time spent shuffling data between host and accelerator.
• Better utilization of GPU cycles for AI computation.
• Easier programming models because memory coherency reduces software complexity.

When you need to stream training data into a GPU or let a CPU handle dynamic scheduling tasks while the GPU crunches numbers, coherency and low-latency sharing are game-changers.

What bi-directional coherent sharing means in practice

Imagine a training loop where part of the preprocessing runs on the CPU while the GPU trains. Instead of copying batches back and forth, they can work from a shared, coherent memory region. That removes copy overhead and reduces stalls, which translates directly into faster iteration and lower cost per training run.

🔗 Networking and offload: ConnectX-9 and BlueField-4

Computation is necessary but not sufficient. Large models need data—and lots of it—delivered consistently. This is where the ConnectX-9 SuperNIC and BlueField-4 DPU become indispensable.

The ConnectX-9 provides up to 1.6 terabits per second of scale-out bandwidth to each GPU. That is a massive pipe. When multiple GPUs need to exchange gradients for distributed training or stream training data from remote storage, that pipe prevents bottlenecks.

The BlueField-4 DPU is equally important, because not all tasks require the GPU. DPUs offload storage, security, and networking functions so the GPU stays focused on matrix math and tensor operations. Offloading in modern AI systems is critical for two reasons:

• Performance: GPUs retain cycles for model work rather than handling IO and networking chores.
• Security and manageability: DPUs can isolate and secure network and storage stacks without impacting the host OS or GPU drivers.

I often compare the DPU to delegating housekeeping tasks to a trusted lieutenant while the general focuses on strategy. It keeps the command chain efficient and the compute resource focused.

⚡ MV-Link switch: Moving more data than the global internet

One phrase here demands attention: the MV-Link sixth-generation switch is described as moving more data than the global internet. That is deliberately provocative, but it conveys the scale of the fabric required for modern AI.

MV-Link connects multiple compute trays in a tight, low-latency mesh. A single switch can link 18 compute nodes, and the MVL-72 rack assembles those links to scale up to 72 Rubin GPUs operating as one. This enables GPU-to-GPU collective communications at massive scale with the kind of latency and bandwidth characteristics training frameworks require.

For distributed training, the interconnect matters at least as much as raw FLOPS. High-performance collective operations like all-reduce and all-gather are bandwidth bound and latency sensitive. MV-Link’s capacity and topology let thousands of accelerators cooperate with near-linear efficiency in many practical cases.

🌐 Spectrum X Ethernet photonics: the switch for an AI factory

Scaling compute across racks is only the first step. To build AI factories—data centers that behave as a single, orchestrated compute plane—you need an Ethernet fabric that keeps pace. That’s where the Spectrum X switch comes in with co-packaged optics.

Spectrum X is notable for being the first Ethernet switch with 512 lanes and 200 Gbit capable co-packaged optics. Co-packaged optics means the optical engines sit very close to the switch silicon, reducing power and enabling much higher port density than traditional pluggable optics.

Why this matters:

• It enables scale-out of thousands of racks with manageable power and footprint.
• It reduces the latency and cost per bit for connecting remote compute pods.
• It simplifies cabling and system-level integration when combined with high-density switches.

When you combine Spectrum X with MV-Link and compute trays, you get an architecture that can scale from a single rack to an entire AI campus, maintaining consistent performance characteristics as you grow.

🔧 Manufacturing and bring-up: the human story

Technology stories often focus on chips and numbers, but the human and process aspects are just as significant. Delivering a platform like Rubin required deep integration across hardware, firmware, software, and manufacturing.

Key points I find important:

• 15,000 engineer-years since design began. That’s an enormous investment in time and expertise across multiple disciplines.
• Robotic assembly at micro-precision for placing thousands of components on a compute board. Automation here is necessary for yield and repeatability at scale.
• System bring-up that validates not just chip function but full-stack coherency, fabric routing, DPU offload, and software orchestration.

These activities translate to faster iteration cycles for customers. When a compute building block has been validated at the factory to a high degree, data centers can deploy faster and with lower operational risk.

📊 The headline numbers

Concrete figures help ground the architecture into real-world expectations. Here are the key specs that illustrate how significant this platform is:

• Six breakthrough chips integrated into the platform.
• 18 compute trays and 9 MV-Link switch trays in the first MVL-72 rack configuration.
• 100 petaflops of AI performance for certain configurations—about five times the prior generation.
• 1.6 terabits per second of scale-out bandwidth per GPU via ConnectX-9.
• 512 lanes and 200 Gbit capable co-packaged optics in the Spectrum X switch.
• 220 trillion transistors across the assembled system, weighing nearly two tons when configured in full racks.

These numbers are not just showpieces; they define the operational envelope for scaling models beyond what previous generations could reasonably support.

🧠 What Rubin enables for AI models

I consider three practical outcomes that follow directly from Rubin’s design choices.

1. Faster iteration for large models

Training very large models depends on both compute and the ability to move gradients and parameters quickly between devices. With coherent CPU-GPU memory sharing and multi-terabit links, model training iterations complete faster. Faster iterations mean more experiments, quicker convergence, and ultimately better models.

2. Efficient inference at scale

When models move to production, inference costs dominate. High-bandwidth NICs, DPUs offloading network and storage services, and an efficient rack-level architecture reduce the cost per inference. Systems that reduce I/O stalls and keep accelerators busy directly cut operational expense.

3. A platform for heterogeneous and multimodal workloads

AI today is increasingly multimodal: text, images, video, audio, and simulation data combined. A platform that integrates fast compute, high I/O, and coherent memory makes it practical to stream diverse data types into model pipelines without excessive preprocessing or bottlenecks.

🧭 Real-world use cases and scenarios

Rubin’s architecture is valuable across many domains. Here are a few that illustrate the breadth of impact:

• Large language models: Training LLMs with hundreds of billions or trillions of parameters benefits from the scale-out fabric and tight GPU cooperation.
• Generative AI and multimodal synthesis: Models that combine images, video, and text need high bandwidth to feed training and inference pipelines.
• Scientific simulation and discovery: Large-scale simulations, from climate models to physics simulations, demand both compute and fast interconnect for distributed solvers.
• Real-time personalization and edge-scale inference: With offloads for networking and storage, Rubin can serve models that require both low latency and high throughput.

I often think about infrastructure choices in terms of bottlenecks. Rubin reduces several common bottlenecks—host-GPU transfers, inter-GPU collective bandwidth, and I/O handling—making these workloads more predictable and cost-effective.

🔍 The trade-offs and considerations

No architecture is without trade-offs, and Rubin is optimized for a specific set of priorities: maximum scale, coherent memory, and turnkey deployment at datacenter scale.

Here are considerations I would weigh:

• Integration vs. flexibility: Highly co-designed systems can be harder to retrofit with third-party components. Organizations with extreme custom requirements should evaluate integration needs carefully.
• Operational model: The compute trays, MV-Link fabrics, and Spectrum-X photonics imply a particular operational model optimized for dense AI deployments. Enterprises should consider whether they want to adopt that model or maintain more heterogeneous fleets.
• Upfront investment: Large-scale systems carry higher upfront costs, but the goal is cost per training run or inference. For organizations running many large workloads, the amortized cost can be compelling.

In short, Rubin targets operators and researchers who need to push AI workloads at the leading edge. For them, the system-level optimizations are precisely what unlocks new model capabilities.

🛠️ Software and orchestration

Hardware is necessary but incomplete without software that understands and exploits it. Rubin’s value depends on the software stack—from low-level drivers enabling coherent memory to orchestration layers that manage distributed training across thousands of GPUs.

Key software responsibilities include:

• Device driver and firmware integration to enable coherent CPU-GPU memory and NVLink fabric management.
• Distributed training frameworks that exploit high-bandwidth collective operations and device affinities.
• Storage and security stacks managed by the DPU so the host CPU and GPU remain focused on AI work.
• Orchestration and scheduling for efficient placement of parallel workloads across compute trays and racks.

When these layers are designed together with the hardware, the platform achieves the high utilization and low overhead necessary to justify the investments in silicon and cabling.

📈 The long arc: What this means for AI infrastructure

Rubin is another step in a trend toward systems optimized for specific workloads rather than general-purpose computing. I see three enduring implications:

1. Consolidation of heterogeneous functions

DPUs, SuperNICs, and co-packaged photonics mean that functions once scattered across host NICs, smart NICs, and separate appliances are now consolidated into the compute plane. Consolidation reduces latency and simplifies management.

2. Systems-oriented performance

Component-level performance is less relevant than system-level throughput and utilization. Coherent memory, massive fabric bandwidth, and offloads produce meaningful system-level improvements that accelerate real work.

3. Infrastructure as a differentiator

Companies that can invest in and operate large, integrated platforms will have a competitive edge for massive model training and inference. This is partly an economic story and partly a technical one: fewer bottlenecks translate directly into better model outcomes per dollar.

💬 A moment of perspective

It is worth pausing on the scale of effort behind Rubin. Building a system that integrates six new chips and validates their combined behavior across thousands of parts is as much a project management and systems engineering feat as a chip design achievement. The emphasis on co-design from silicon up through network and software is what creates a platform rather than a set of parts.

Rubin is here.

That line captures more than product availability. It is shorthand for a shift in how I expect AI infrastructure will be delivered: holistic, co-designed, and optimized for the workflows that matter today.

🔮 Looking forward

I predict several near-term impacts from the Rubin Platform:

• Faster model iteration cycles for research labs and enterprise teams undertaking ambitious R&D.
• Lower marginal cost for large-scale training and inference as fabrics become more efficient and DPUs handle mundane tasks.
• Accelerated adoption of multimodal and simulation-driven AI use cases that need both compute density and predictable data movement.

Longer term, Rubin-like architectures will push the ecosystem to rely more on system-level metrics—utilization, time-to-train, and cost-per-inference—when making infrastructure decisions.

✅ Final thoughts

I believe the Rubin Platform represents a pivot: from incremental component improvements to synchronized, system-level innovation. By designing CPU, GPU, NIC, DPU, NVLink fabric, and photonics together, the platform addresses the real bottlenecks of modern AI—data movement, I/O offload, and scale-out orchestration.

For teams building the next generation of language models, multimodal systems, and large-scale simulations, Rubin offers an architectural path to higher performance and lower operational friction. For the broader industry, it raises the bar on what an AI supercomputer can be—a tightly integrated, scalable, and manufacturable platform that treats data movement with the same engineering rigor as compute.

There are trade-offs, as always, but the potential is clear: when the entire stack is optimized together, the next frontier of AI becomes not only visible but attainable.